Silexica contributes to SHIM 2.0

Major Silexica contribution to new architecture description


El Dorado Hills, CA – October 24, 2016 – The Multicore Association™ (MCA), a global non-profit organization that develops standards to optimize products with multicore processor implementations, announced today that it is underway in developing an updated version of its Software/Hardware Interface for Multicore/Manycore (SHIM) processors and tools. SHIM version 1.0, which was available in 2015, is a specification that helps existing software tools quickly adopt to new hardware and accelerates the development of new innovative tools.

SHIM’s primary goal is to define an architecture description standard useful for software design (analogous to the hardware description format called IP-XACT, which is used for hardware design). Some architectural features that SHIM describes include processor cores, accelerators, memory/caches and inter-core communication channels – providing details such as instruction, memory, and communication performance information.

The SHIM standard is beneficial for many types of tools, including performance estimation, system configuration, and hardware modeling. Performance information is critical for most software development tools, including performance analysis and optimization tools and auto-parallelizing compilers.

The initial updates to be included in SHIM 2.0 will come from Silexica, an MCA member. “Silexica has a lot of experience in abstract hardware modeling, reflected in in its own automated software modeling tool for multicore software developers and HW/SW system architects,” said Maximilian Odendahl, CEO of Silexica. “As a result, we have determined that the SHIM 2.0 should include enhanced capabilities for improved performance estimation accuracy. SHIM 2.0 will be able to model state-of-the art processors including heterogeneous functional units, pipelining effects, and 32-bits vs. 64-bits, and single-instruction-multiple-data instructions (SIMD). This capability will allow to support the description of complex DSPs, hardware accelerators, and soft cores. The SHIM 2.0 will also support more accurate modeling of power consumption, allowing the use of different voltages and frequencies associated with individual processor or clusters.”

The Multicore Association working group that is developing the SHIM specification is chaired by Masaki Gondo, Software CTO and GM of Technology at eSOL. “After the completion of SHIM 1.0, eSOL was among the first companies to implement a product utilizing the standard,” said Masaki Gondo. “The eSOL Model-Based Parallelizer (MBP) tool estimates code execution performance based on architecture and performance information for the multi- or many-core processor to be implemented. Utilizing the XML-based SHIM, MBP automatically generates parallel code by allocating blocks that have been grouped on the basis of this information to separate cores.”

Inquiries regarding membership in the Multicore Association and participation in this and other working groups should be made to Markus Levy. The SHIM specification is publicly available from the organizations website. The working group aims to release SHIM 2.0 in Q3 of 2017. For more information, visit

About The Multicore Association

The Multicore Association provides a neutral forum for vendors interested in, working with, and/or proliferating multicore-related products, including processors, infrastructure, devices, software, and applications. The consortium has made freely available its SHIM, Multicore Communications API (MCAPI) Multicore Resource Management API (MRAPI), and Multicore Task Management (MTAPI) specifications, as well as its Multicore Programming Practices (MPP) guide. In addition to the SHIM working group, the organization has active working groups focused on OpenAMP and Multicore Communications (Version 3.x). Further information is available at

Markus Levy

The Multicore Association

+1 530 672-9113


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