Heterogeneous Multicore Design Automation: Current and Future
Multicore systems with complex architectural features such as heterogeneous processors and sophisticated power management are widely deployed in virtually all computing segments now. Not only processing elements (processors) but also memories and interconnects have become heterogeneous. This makes designing software for such systems extremely difficult, considering the huge design space to consider for all kinds of tradeoffs such as performance and area/power. This tutorial presents state-of-the-art multicore software design tools (SLX Toolsuite from Silexica) to demonstrate the current industrial capabilities to address such a challenge. An industrial perspective will also be provided by a leading wireless company, giving a preview of the challenges that will come in the next 5-10 years with the next wave of multicore design. As innovation often comes from academia firstly, this tutorial will also discuss research results to give another angle looking at the same multicore design challenges.
- Weihua Sheng (Silexica)
- Xiaotao Chen (Huawei Technologies)
- Jeronimo Castrillon (TU Dresden)
Agenda on January 27, 2017
- 10:00 - 10:20 Weihua Sheng (Silexica) "State-of-the-art multicore design tools"
- 10:20 - 11:00 Xiaotao Chen (Huawei) "System Level Performance and Power Co-Optimization for Heterogeneous Multicore SoC"
- 11:00 - 11:30 Jeronimo Castrillon (Dresden) "Flexible and scalable dataflow programming for manycores"
- 11:30 - 11:45 Coffee break
- 11:45 - 12:30 SLX Tools Demo
- 12:30 - 12:45 Q&A
Weihua Sheng (Silexica) "State-of-the-art multicore design tools"
Modern software applications increasingly push processor boundaries. The industry has responded by moving to multicore architectures. Multicore development techniques and tools, however, have not experienced the same levels of innovation and progress. Multicore software applications are generally programmed with time-consuming and complex manual techniques that can’t accommodate the exponential growth in the number of required processor cores. Without Software Design Automation tools, this design complexity can’t be solved. An overview on the state-of-the-art multicore design tools will be given in this talk with some concrete examples. Listen to Weihua introducing his tutorial.
Xiaotao Chen (Huawei) "System Level Performance and Power Co-Optimization for Heterogeneous Multicore SoC"
Meeting Power budget has been a top challenge in Baseband SoC Design Flow since 3G/4G. The situation is getting worse for the next generation SoC towards 4.5G/5G at new technology nodes. System level power estimation and optimization are playing a much bigger role to meet SoC Power efficiency goals, both at Behavioral and Architectural Levels according to industry predictions. Systematic co-optimization is our answer for current and future power and performance challenges. The System level profiling and optimization toolset achieved surprising improvement in both performance and power efficiency over traditional approaches, from processing units (DSP/CPU) power analysis to network-on-chip power efficiency, all the way to power-aware mapping and scheduling of heterogeneous and hierarchical architectures for our Wireless Baseband applications.
Jeronimo Castrillon (Dresden) "Flexible and scalable dataflow programming for manycores"
Dataflow-based programming have proven to be a good programming model for heterogeneous multi-processor systems on chip in the signal processing and multimedia domains. This is due to a clear separation of computation and communication, well-defined semantics and a strict distributed state. However, for larger manycore systems, running multiple applications, dataflow programming flows face several challenges. On the one hand, programming for thousands of cores requires more scalable programming abstractions and mapping algorithms. On the other hand, traditional fixed mappings have to become flexible in order to adapt to the resources available at load time, when running alongside other applications. This talk discusses how to implicitly define scalable graphs and an algorithmic approach for scalable and flexible mappings.